1. Field of the Invention
The present invention generally relates to the design and fabrication of integrated circuit chips from silicon wafers, and more particularly to a method of correcting deficiencies in an integrated circuit design which is manufactured using circuit pattern masks and photolithography.
2. Description of the Related Art
Integrated circuits are used for a wide variety of electronic applications, from simple devices such as wristwatches, to the most complex computer systems. A microelectronic integrated circuit (IC) chip can generally be thought of as a collection of logic cells with electrical interconnections between the cells, formed on a semiconductor substrate (e.g., silicon). An IC may include a very large number of cells and require complicated connections between the cells. A cell is a group of one or more circuit elements such as transistors, capacitors, resistors, inductors, and other basic circuit elements combined to perform a logic function. Cell types include, for example, core cells, scan cells, input/output (I/O) cells, and memory (storage) cells. Each of the cells of an IC may have one or more pins, each of which in turn may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip. For more complex designs, there are typically at least four distinct layers of conducting media available for routing, such as a polysilicon layer and three metal layers (metal-1, metal-2, and metal-3). The polysilicon layer, metal-1, metal-2, and metal-3 are all used for vertical and/or horizontal routing.
An IC chip is fabricated by first conceiving the logical circuit description, and then converting that logical description into a physical description, or geometric layout. This process is usually carried out using a “netlist,” which is a record of all of the nets, or interconnections, between the cell pins, including information about the various components such as transistors, resistors and capacitors. A layout typically consists of a set of planar geometric shapes in several layers. The layout is then checked to ensure that it meets all of the design requirements, particularly timing requirements. The result is a set of design files known as an intermediate form that describes the layout. The design files are then run through a dataprep process that is used to produce patterns called masks by an optical or electron beam pattern generator. During fabrication, these masks are used to etch or deposit features in a silicon wafer in a sequence of photolithographic steps using a complex lens system that shrinks the mask image. The process of converting the specifications of an electrical circuit into such a layout is called the physical design.
Chip performance and yield are increasingly limited by systematic and random variations introduced during wafer processing. Systematic variations are layout-dependent and can be broadly classified as optical and non-optical in nature. Optical effects have their origin in the photolithographic process steps including mask, resolution enhancement techniques and resist, and are well-modeled in conventional lithography simulators. Optical effects such as pitch-dependent line width variations, flare, corner rounding and line-end shortening all affect electrical properties of devices forming the integrated circuit, and can easily render a chip defective. Optical effects can be mitigated by methods such as optical proximity correction, phase shift masking, and sub-resolution assist feature insertion.
Optical proximity correction (OPC) compensates for optical effects by adjusting the edges of the polygons forming a pattern mask, as illustrated in FIG. 1. The polygons are typically rectangles or other shapes (L-, U-, Z-) that may be decomposed into rectangles whose length and width directions are respectively parallel with the orthogonal x- and y-axes of the coordinate system that lays out the chip. In the example of FIG. 1 different sections of the edges for an integrated circuit pattern mask design 2 are moved inwardly or outwardly depending on the optical effect encountered, to yield a distorted pattern mask design 2′. OPC is carried out by simulating optical lithographic fabrication taking into consideration various optical effects at different stages in the process. The resulting simulated contour is then compared to the target contour and edge placement errors are identified. The objective is to minimize edge placement errors arising from all of the optical steps. While OPC is useful in reducing optical variations, it has its limitations. Minimizing edge placement errors does not necessarily guarantee the best electrical behavior, and non-ideal electrical behavior will adversely affect cell leakage and circuit timing.
Non-optical effects are layout-dependent systematic variations which originate from processes other than lithography. Some examples of non-optical effects are stress variations, well-proximity effect, spacer thickness variations, and rapid thermal anneal (RTA) variations. There is no standard technique to compensate for non-optical effects. One approach to modeling some non-optical effects uses a circuit-level simulation tool such as SPICE, which employs numerical integration formulae to form companion models for circuit elements. While circuit simulators like SPICE are straightforward and fairly quick to run, if the simulation is not set up properly the results can be inaccurate. Also, while SPICE models are able to capture layout-dependent variations such as stress and well proximity, other non-optical effects such as spacer thickness and RTA cannot be captured in the device models due to lack of knowledge of the cell neighborhood, and hence these effects cannot be accounted for at design time.
Designers usually rely on a combination of several ad hoc methods to compensate for non-optical effects, e.g., selective gate length biasing, or RX/PC layer fill. Gate length biasing (originally used for leakage control) simply increases a device's size. It can also be used to compensate for certain global systematic variations. However, gate length biasing may produce inaccurate results since it is performed with coarse discrete increments.
In light of the foregoing, it would be desirable to devise an improved method of compensating for systematic variations in integrated circuit chips which arise from non-optical effects. It would be further advantageous if the method could easily be incorporated into a physical design tool which also takes optical effects of the layout into consideration.